The transfer of data between synchronous high speed digital circuits and synchronous low speed digital circuits has typically been achieved by reducing the transfer frequency at the boundary to the rate of the low speed circuits. This transfer frequency reduction can be accomplished through serial to parallel conversion of the data with a strobe being generated from the high speed section to initiate transfer. The transfer rate is limited by the timing resolution of the low speed circuits or by other limiting factors such as propagation delay time, and variations thereof. The slowest link in the path must not exceed the transfer period to insure accurate data transfer. This transfer period is pre-determined based on worse-case design analysis of propagation delays, data acquisition times (setup and hold times), wiring distances and variations of the above due to device process differences, temperature variations, power supply voltages, age of the components and the like.
Due to the many factors involved in the determination of a worse case timing resolution as well as the variations of such a determined resolution as a result of changes in temperature, voltage, production, and the like, typical transfer rates are greatly reduced from the potential rates that could exist given optimal conditions. Such reduced transfer rates limit circuit functionality, and generally increase circuit size and fabrication costs. One major impact is in the number of pins required for very large-scale integrated circuit (VLSI) devices to facilitate a low speed parallel transfer. The data must be divided down to a suitable period of time such that the data transfer period exceeds all timing uncertainties. This typically involves divisors of 4, 8, 16 or higher powers of 2 depending on the data transfer frequency, thereby resulting in corresponding pinout increases.
Packaging limitations in VLSI are the major obstacle in applying semiconductor technology. To date, transistor evolution has far outpaced packaging technology. Large pinout devices are generally not cost effective, consume large board areas and decrease reliability in proportion to the pinout increase. Likewise system constraints on board edge connectors and the numbers of input and output pins greatly favor reducing the number of connections necessary to convey high speed data.
The present invention allows automatic adaptation of the transfer strobe between the high speed and low speed circuits so as to compensate for timing drifts resulting from changes in system component operation induced by variations in temperature, voltage, path delay and the like. This invention thus increases the transfer rate toward an optimal amount, thereby minimizing the number of signal connections by minimizing the size of the parallel data word transferred.
In general, the invention uses additional circuitry and data overhead to communicate instantaneous timing information across the high speed/low speed boundary. Additional synchronization bit sequences (synchronization channel) are added to the desired data stream. This additional synchronization information can be resolved by the low speed circuit to identify boundary conditions. Search algorithms of a general nature are used in conjunction with the transfer strobe to determine if the data is being received correctly. In the event data is corrupted by any of the previously mentioned timing variances, the low speed circuit alerts the high speed circuit to alter its transfer strobe accordingly. Thus automatic in-circuit corrections can be made to compensate for timing variances.
The inverse direction of transfer from low speed to high speed circuitry is accomplished via a similar scheme except the synchronous identification and the tap delay select circuitry are all located in the high speed section. In general, clock select circuits for low speed to high speed interfacing are more straight-forward but the auto-compensating features of this invention allow higher transfer rates with reduced input/output connections. Use of a delay tap in the low speed to high speed direction is typically not required due to the availability of a high speed clock that effectively oversamples the lower speed transfer data. Whole clock increments can be selected to find the optimum strobe position in lieu of selecting finer delay increments.
As data frequencies become higher and packaging limitations grow more severe, the incentives to reduce signal connections outweigh the increase in circuit complexity. Power savings are also a critical concern in telecommunications and other electronic systems. By keeping the complex circuit in the low speed section, technologies such as complimentary metal oxide silicon (CMOS) can be used to minimize power consumption. The high speed circuit which may require emitter coupled logic (ECL) or other high power technologies is therefore simplified in design, not requiring complex functions for implementation.